M.S. in Computer Engineering with great knowledge and passion in hardware FPGA and ASIC design and verification. Involved in numerous RTL design projects utilizing VHDL, Verilog and System Verilog with proven knowledge of synthesis, static timing and state machines. Experienced writing synthesizable Verilog and VHDL code for ASIC & FPGA design with strong debugging skills in both Software and Hardware design. Equipped with two years of research and publication experience with excellent documentation skill.
● Researched an efficient algorithm for blood cell segmentation in microscopic blood images using digital image processing techniques, to improve and accelerate the diagnosis of different hematologic disorders.
● Proposed a novel technique that exploits the correlation between the RGB and CMYK color spaces, and yields segmented nuclei that are virtually congruent to the nuclei in the initial image.
● Developed a highly versatile image processing technique to segment the nuclei from a broad spectrum of blood images while retaining cell features and integrity in the processed image up to 98.99% accuracy using Matlab.
● Self-taught programming languages such as HTML/PHP/CSS/JS to modify the template and edit the content based on personal needs.
● Serves as a platform to showcase artworks driven by personal hobby and interest.
● Assessed the process and made recommendations to implement automated validation tools to supervisors.
● Utilized C# in Visual Studio IDE to develop a software tool that automates data validation, flags invalid or incomplete profile with high accuracy, and reduced human involvement and processing time up to 95%.
● Implemented a simplified messenger in Visual Studio IDE utilizing Distance Vector Routing Protocol using TCP/IP protocol to determine the best route between nodes in the network.
● Predefined network topology is loaded into the program upon startup, and server commands may be called to manipulate the topology, including updating the link cost between two nodes and disabling certain nodes.
● Developed a two-in-one server-client chat application utilizing TCP/IP protocol in C language in Eclipse and UNIX shell that is able to handle multiple socket connections at any runtime.
● Extended program functionality with user commands, and handled possible system and user errors in the program.
● White Blood Cells detection and calculation on color blood test images.
● Morphological operation to process and filter image noise for further handling.
● Translated concept for implementation on real-time detection on FPGA.
● Modeled a working RISC-Y processor that has immediate or direct addressing mode, by instantiating modules such as scalable MUXs and registers, sequence controller, scalable register files, AASD and ALU.
● Wrote a testbench to verify the functionalities of the processor module: fetch an instruction from the ROM memory, decode the instruction, fetch a data operand, perform ALU operations and store the result.
● Implemented FSM on the FPGA for chess clocks and timers with error handlings.
● Added Seven-segment displays for two user’s countdowns, with on-board LEDs.
● Implemented LFSR for pseudo-random number generation for Fischer chess clock.
● Implemented the Optical Recognition System using Matlab to extract the musical data such as frequency and duration of the note from a camera image, which they will be stored into a SD memory card.
● Configured SDIO to read the data, and store them into BRAM within the Zedboard with read and write functionalities defined in the software implementations.
● Utilized ADAU1761 Audio Codec and I2C communication protocol for sound reproduction at the speaker connected through GPIO pin. 8 onboard LEDS are used for pitch visualization of the current playing note.
● Integrated PL and PS of the board to implement functionality for audio streaming.
● Added frequency filtering and tones to the audio streaming output.
● Implemented onboard display and switches for better user experience and control.
● Implemented floating point adder in VHDL according to IEEE 754 standard.
● The adder accepts and normalizes two numbers, and using two’s complement adder to add or subtract the pre-normalized significands.
● The design is simulated and tested using Xilinx Vivado software.